Intel Pch Watchdog Controller Driver

I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture.It is designed to be paired with a second support chip known as a northbridge.As with any other southbridge, the ICH is used to connect and control peripheral devices. When you find the program Intel® Watchdog Timer Driver (Intel® WDT), click it, and then do one of the following: Windows Vista/7/8: Click Uninstall. Windows XP: Click the Remove or Change/Remove tab (to the right of the program). Follow the prompts. A progress bar shows you how long it will take to remove Intel Watchdog Timer Driver Intel WDT. Wi Fi Not Working in PM 7 on HP Notebook [SOLVED and CLOSED] Home; Help. Subsystem: Hewlett-Packard Company Wildcat Point-LP Thermal Management Controller Kernel driver in use: intel_pch_thermal Kernel modules. Set debug level (0-5) (default 0) (int) parm: disable_watchdog:Set to 1 to disable the watchdog (default 0) (bool. IBASE MB970F LGA1155 B75 intel Pentium ATX motherboard w/ Intel® Q77 PCH w/ DVI-I, DVI-D, DisplayPort. Watchdog timer, Digital I/O, iAMT (8.0), vPro. Intel USB 3.0 drivers for Windows 7 64bit. Intel® USB 3.0 eXtensible Host Controller Driver for 3rd generation Intel® Core™ Processor Family, 2nd generation Intel® Core™ i3 processor, 2nd generation Intel® Core™ i5 processor, 2nd generation Intel® Core™ i5 vPro™ processor, 2nd generation Intel® Core™ i7 processor, 2nd generation Intel® Core™ i7 vPro™ processor and Intel.

  1. Intel Pch Watchdog Controller Driver Download
  2. Intel Network Controller Drivers
  3. Intel Pch Watchdog Controller Driver Update
  4. Intel Pch Watchdog Controller Driver Windows 10
Block diagram of the Platform Controller Hub–based chipset architecture
An Intel DH82H81 PCH with its die exposed

The Platform Controller Hub (PCH) is a family of Intelchipsets, introduced circa 2008. It is the successor to the Intel Hub Architecture, which used a northbridge and southbridge instead, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

  • 1Overview
  • 2Ibex Peak
  • 6Cougar Point
  • 12Lynx Point

Overview[edit]

The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.[1]

Under the Hub Architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the memory controller and PCI Express lanes for expansion cards, are now incorporated into the CPU die or package.

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions. The system clock was previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets.

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With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

This style began in Nehalem and will remain for the foreseeable future, through Cannon Lake.

Intel Pch Watchdog Controller Driver Download

Phase-out[edit]

Beginning with ultra-low-power Broadwells and continuing with mobile Skylake processors, Intel incorporated the clock, PCI controller, and southbridge IO controllers into the CPU package, eliminating the PCH for a system on a chip (SOC) design. Rather than DMI, these SOCs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.[needs update]

Ibex Peak[edit]

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:

  • BD3400 (PCH 3400) Server
  • BD3420 (PCH 3420) Server
  • BD3450 (PCH 3450) Server
  • BD82P55 (PCH P55) Desktop Base
  • BD82H55 (PCH H55) Desktop Home
  • BD82H57 (PCH H57) Desktop Home
  • BD82Q57 (PCH Q57) Desktop Office
  • BD82PM55 (PCH PM55) Mobile Base
  • BD82HM55 (PCH HM55) Mobile Home
  • BD82HM57 (PCH HM57) Mobile Home
  • BD82QM57 (PCH QM57) Mobile Office
  • BD82QS57 (PCH QS57) Mobile SFF

Issues[edit]

  • Bogus USB ports will be detected by desktop PCHs equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Applying AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
  • Bogus USB ports will be detected by mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Applying AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
  • Reading the HPET comparator timer immediately after a write returns the old value (erratum 14)
  • SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell[edit]

Langwell is the codename of a PCH in the MoorestownMID/smartphone platform.[2][3] for AtomLincroft microprocessors.

This has the following variations:

  • AF82MP20 (PCH MP20)
  • AF82MP30 (PCH MP30)

Tiger Point[edit]

Pch
Intel CG82NM10

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for AtomPineview microprocessors.

This has the following variations:

  • CG82NM10 (PCH NM10)

Topcliff[edit]

Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for AtomTunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

  • CS82TPCF (PCH EG20T)

Cougar Point[edit]

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

  • BD82C202 (PCH C202) Server
  • BD82C204 (PCH C204) Server
  • BD82C206 (PCH C206) Workstation / Server
  • BD82P67 (PCH P67) Desktop Base
  • BD82H67 (PCH H67) Desktop Home
  • BD82H61 (PCH H61) Desktop Home
  • BD82Z68 (PCH Z68) Combined desktop base and home
  • BD82B65 (PCH B65) Desktop Office
  • BD82Q67 (PCH Q67) Desktop Office
  • BD82Q65 (PCH Q65) Desktop Office
  • BD82HM65 (PCH HM65) Mobile Home
  • BD82HM67 (PCH HM67) Mobile Home
  • BD82QM67 (PCH QM67) Mobile Office
  • BD82QS67 (PCH QS67) Mobile SFF
  • BD82UM67 (PCH UM67) Ultra Mobile

Issues[edit]

In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. The bug was present in revision B2 of the chipsets, and was fixed with B3. Z77 did not have this bug,since the B2 revision for it was never released. 6Gbit/s ports were not affected. This bug was especially a problem with the H61 chipset, which only had 3Gbit/s SATA ports. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[4][5]

Whitney Point[edit]

Whitney Point is the codename of a PCH in the Oak Trail tablet platform for AtomLincroft microprocessors.

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This has the following variations:

  • 82SM35 (PCH SM35)

Panther Point[edit]

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets (except PCH HM75) have integrated USB 3.0.[6]

This has the following variations:

  • BD82C216 (PCH C216) Workstation/Server
  • BD82H77 (PCH H77) Desktop Home
  • BD82Z77 (PCH Z77) Combined desktop base and home
  • BD82Z75 (PCH Z75) Combined desktop base and home
  • BD82B75 (PCH B75) Desktop Office
  • BD82Q77 (PCH Q77) Desktop Office
  • BD82Q75 (PCH Q75) Desktop Office
  • BD82HM77 (PCH HM77) Mobile Home
  • BD82HM76 (PCH HM76) Mobile Home
  • BD82HM75 (PCH HM75) Mobile Home
  • BD82HM70 (PCH HM70) Mobile Home
  • BD82QM77 (PCH QM77) Mobile Office
  • BD82QS77 (PCH QS77) Mobile Office
  • BD82UM77 (PCH UM77) Ultra Mobile

Cave Creek[edit]

Cave Creek is the codename of the PCH most closely associated with Crystal Forest platforms and Gladden[7] or Sandy Bridge-EP/EN[8] processors.

  • DH8900 (PCH 8900) Communications
  • DH8903 (PCH 8903) Communications
  • DH8910 (PCH 8910) Communications
  • DH8920 (PCH 8920) Communications

Patsburg[edit]

Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms.[9] Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.[10]

Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[11][12]

Patsburg has the following variations:

  • BD82C602 (PCH C602) Server
  • BD82C602J (PCH C602J) Server
  • BD82C604 (PCH C604) Server
  • BD82C606 (PCH C606) Workstation / Server
  • BD82C608 (PCH C608) Workstation / Server
  • BD82X79 (PCH X79) Workstation

Coleto Creek[edit]

Coleto Creek is the codename of the PCH most closely associated with Highland Forest platforms and Ivy Bridge-EP[13] processors.

  • DH8925 (PCH 8925) Communications
  • DH8926 (PCH 8926) Communications
  • DH8950 (PCH 8950) Communications
  • DH8955 (PCH 8955) Communications

Lynx Point[edit]

Lynx Point is the codename of a PCH in Intel 8 Series chipsets, most closely associated with Haswell processors with LGA 1150 socket.[14] The Lynx Point chipset connects to the processor primarily over the Direct Media Interface (DMI) interface.[15]

The following variants are available:[16]

  • DH82C222 (PCH C222) Workstation/Server
  • DH82C224 (PCH C224) Workstation/Server
  • DH82C226 (PCH C226) Workstation/Server
  • DH82H81 (PCH H81) Desktop Home
  • DH82H87 (PCH H87) Desktop Home
  • DH82Z87 (PCH Z87) Combined desktop base and home
  • DH82B85 (PCH B85) Desktop Office
  • DH82Q87 (PCH Q87) Desktop Office
  • DH82Q85 (PCH Q85) Desktop Office
  • DH82HM87 (PCH HM87) Mobile Home
  • DH82HM86 (PCH HM86) Mobile Home
  • DH82QM87 (PCH QM87) Mobile Office

In addition the following newer variants are available, additionally known as Wildcat Point, which also support Haswell Refresh processors:[17]

  • DH82H97 (PCH H97) Desktop Home
  • DH82Z97 (PCH Z97) Combined desktop base and home

Issues[edit]

A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[18][19] This issue is corrected in C2 stepping level of the Lynx Point chipset.[20]

Wellsburg[edit]

Intel Network Controller Drivers

Wellsburg is the codename for the C610-series PCH, supporting the Haswell-E (Core i7 Extreme), Haswell-EP (Xeon E5-16xx v3 and Xeon E5-26xx v3), and Broadwell-EP (Xeon E5-26xx v4) processors. Generally similar to Patsburg, Wellsburg consumes only up to 7 W when fully loaded.[21]

Wellsburg has the following variations:

  • DH82029 (PCH C612), intended for servers and workstations
  • DHX99 (PCH X99), intended for enthusiasts making use of Intel Core i7 59/69XX processors but it is compatible with LGA 2011-3Xeons.

Sunrise Point[edit]

Sunrise Point is the codename of a PCH in Intel 100 Series chipsets, most closely associated with Skylake processors with LGA 1151 socket.

The following variants are available:[22]

  • GL82C236 (PCH C236) Workstation/Server
  • GL82H110 (PCH H110) Desktop Home
  • GL82H170 (PCH H170) Desktop Home (Note the datasheet linked one that page is incorrect, see via PCH HM170 below)
  • GL82Z170 (PCH Z170) Combined desktop base and home
  • GL82B150 (PCH B150) Desktop Office
  • GL82Q150 (PCH Q150) Desktop Office
  • GL82Q170 (PCH Q170) Desktop Office
  • GL82HM170 (PCH HM170) Mobile Home
  • GL82CM236 (PCH CM236) Mobile Workstation
  • GL82QM170 (PCH QM170) Mobile Office

Union Point[edit]

Union Point is the codename of a PCH in Intel 200 Series chipsets, most closely associated with Kaby Lake processors with LGA 1151 socket.

The following variants are available:[23]

  • GL82H270 (PCH H270) Desktop Home
  • GL82Z270 (PCH Z270) Combined desktop base and home
  • GL82B250 (PCH B250) Desktop Office
  • GL82Q250 (PCH Q250) Desktop Office
  • GL82Q270 (PCH Q270) Desktop Office

Lewisburg[edit]

Lewisburg is the codename for the C620-series PCH, supporting LGA 2066 socketed Skylake-X/Kaby Lake-X processors ('Skylake-W' Xeon).

Lewisburg has the following variations:

  • EY82C621 (PCH C621), intended for servers and workstations
  • EY82C622 (PCH C622), intended for servers and workstations
  • EY82C624 (PCH C624), intended for servers and workstations
  • EY82C625 (PCH C625), intended for servers and workstations
  • EY82C626 (PCH C626), intended for servers and workstations
  • EY82C627 (PCH C627), intended for servers and workstations
  • EY82C628 (PCH C628), intended for servers and workstations

Basin Falls[edit]

Basin Falls is the codename for the C400-series PCH, supporting Skylake-X/Kaby Lake-X processors (branded Core i9 Extreme and 'Skylake-W' Xeon). Generally similar to Wellsburg, Basin Falls consumes only up to 6 W when fully loaded.

Basin Falls has the following variations:

  • GL82C422 (PCH C422), intended for servers and workstations
  • GL82X299 (PCH X299), intended for enthusiasts making use of Intel Core i9 76-79XX processors but it is compatible with LGA 2066Xeons.

Cannon Point[edit]

Cannon Point is the codename of a PCH in Intel 300 Series chipsets, most closely associated with Coffee Lake processors with LGA 1151 socket.[24]

The following variants are available:[25]

  • FH82H310 (PCH H310) Desktop Home
  • FH82H370 (PCH H370) Desktop Home
  • FH82Z370 (PCH Z370) Combined desktop base and home
  • FH82B370 (PCH B360) Desktop Office
  • FH82Q370 (PCH Q370) Desktop Office
  • FH82HM370 (PCH HM370) Mobile Home
  • FH82QM370 (PCH QM370) Mobile Office
  • FH82CM246 (PCH CM246) Mobile Workstation

See also[edit]

  • System Controller Hub (SCH)
  • I/O Controller Hub (ICH)
  • PCI IDE ISA Xcelerator (PIIX)
  • Intel Management Engine (ME)

References[edit]

  1. ^Hook, Brian. 'Breaking the Speed Barrier: The Frontside Bus Bottleneck'. Technewsworld. Retrieved 1 February 2016.
  2. ^Langwell Background Information, Intel, archived from the original on 2012-07-09, retrieved 2010-08-03
  3. ^New Intel Atom Processor-Based Platform Using Significantly Lower Power Readies Intel for Smartphone, Tablet Push, Intel, May 4, 2010, retrieved 2010-07-27
  4. ^Intel Identifies Chipset Design Error, Implementing Solution, Intel, 31 January 2011
  5. ^The Source of Intel's Cougar Point SATA Bug, AnandTech, 31 January 2011
  6. ^'Correction: Ivy Bridge and Thunderbolt - Featured, not Integrated'. AnandTech. Retrieved 2014-01-21.
  7. ^(2:48) (2014-01-13). 'Intel Xeon/Core/Pentium/Celeron, Communications Chipset 89xx'. Intel. Retrieved 2014-01-21.
  8. ^'Intel Xeon Processor E5-2600/E5-2400/Communications Chipset 89xx'. Ssl.intel.com. Retrieved 2014-01-21.
  9. ^'A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay', vr-zone.com, April 15, 2010, archived from the original on April 23, 2010, retrieved 2010-07-27
  10. ^'Intel plugs both your sockets with 'Jaketown' Xeon E5-2600s • The Channel'. Channelregister.co.uk. 2012-03-06. Retrieved 2014-01-21.
  11. ^'Ivy Bridge-E Not a Cut-down 8-core, 20 MB LLC Die'. techPowerUp.com. 2013-08-12. Retrieved 2014-01-21.
  12. ^https://www.theregister.co.uk/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/
  13. ^'Intel Announces Highland Forest, a New Platform that will Accelerate Network Transformation'. Intel. 2013-12-04. Retrieved 2014-08-09.
  14. ^Shawn Knight (2012-11-13). 'Leaked Intel slides detail Haswell's Lynx Point chipset'. techspot.com. Retrieved 2013-10-30.
  15. ^'Intel 'Lynx Point' 8-series Chipset Detailed, Completely SATA 6 Gbit/s'. techpowerup.com. 2012-02-17. Retrieved 2013-10-30.
  16. ^'Products (Formerly Lynx Point)'. Intel. Retrieved 2013-10-30.
  17. ^Andrew Cunningham (2014-05-11). 'New Intel chipsets speed up your storage, but they're missing new CPUs'. arstechnica.com. Retrieved 2014-05-13.
  18. ^'Lynx Point USB 3.0 Controller Issue Correction Needs New Hardware'. techpowerup.com. 2013-03-11. Retrieved 2013-10-30.
  19. ^Frank Everaardt (2013-03-01). 'USB 3.0 problems for Intel's Haswell'. hardware.info. Retrieved 2013-10-30.
  20. ^'Haswell C2 stepping availability'. arstechnica.com. 2013. Retrieved 2013-10-30.
  21. ^'Intel Readies 18-Core Xeon 'Broadwell-EP' Microprocessors for Launch in 2015 – Report'. xbitlabs.com. Archived from the original on 2013-12-24. Retrieved 2014-01-21.
  22. ^'Products (Formerly Skylake)'. Intel. Retrieved 2015-10-24.
  23. ^'Products (Formerly Kaby Lake)'. Intel. Retrieved 2017-08-18.
  24. ^Shilov, Anton (April 26, 2018). 'Intel Outs Z390 & X399 PCHs for Cannon Lake & Coffee Lake CPUs'. AnandTech. Retrieved 2018-06-29.
  25. ^'Products (Formerly Coffee Lake)'. Intel. Retrieved 2018-06-29.
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groeckwatchdog: iTCO_wdt: Various improvements77d9f76May 6, 2019
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Intel Pch Watchdog Controller Driver Update

/*
* intel TCO Watchdog Driver
*
* (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
* provide warranty for any of this software. This material is
* provided 'AS-IS' and at no charge.
*
* The TCO watchdog is implemented in the following I/O controller hubs:
* (See the intel documentation on http://developer.intel.com.)
* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
* document number 290687-002, 298242-027: 82801BA (ICH2)
* document number 290733-003, 290739-013: 82801CA (ICH3-S)
* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
* document number 290744-001, 290745-025: 82801DB (ICH4)
* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
* document number 273599-001, 273645-002: 82801E (C-ICH)
* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
* document number 300641-004, 300884-013: 6300ESB
* document number 301473-002, 301474-026: 82801F (ICH6)
* document number 313082-001, 313075-006: 631xESB, 632xESB
* document number 307013-003, 307014-024: 82801G (ICH7)
* document number 322896-001, 322897-001: NM10
* document number 313056-003, 313057-017: 82801H (ICH8)
* document number 316972-004, 316973-012: 82801I (ICH9)
* document number 319973-002, 319974-002: 82801J (ICH10)
* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
* document number 320066-003, 320257-008: EP80597 (IICH)
* document number 324645-001, 324646-001: Cougar Point (CPT)
* document number TBD : Patsburg (PBG)
* document number TBD : DH89xxCC
* document number TBD : Panther Point
* document number TBD : Lynx Point
* document number TBD : Lynx Point-LP
*/
/*
* Includes, defines, variables, module parameters, ..
*/
#definepr_fmt(fmt) KBUILD_MODNAME ': ' fmt
/* Module and version information */
#defineDRV_NAME'iTCO_wdt'
#defineDRV_VERSION'1.11'
/* Includes */
#include<linux/acpi.h>/* For ACPI support */
#include<linux/module.h>/* For module specific items */
#include<linux/moduleparam.h>/* For new moduleparam's */
#include<linux/types.h>/* For standard types (like size_t) */
#include<linux/errno.h>/* For the -ENODEV/.. values */
#include<linux/kernel.h>/* For printk/panic/.. */
#include<linux/watchdog.h>/* For the watchdog specific items */
#include<linux/init.h>/* For __init/__exit/.. */
#include<linux/fs.h>/* For file operations */
#include<linux/platform_device.h>/* For platform_driver framework */
#include<linux/pci.h>/* For pci functions */
#include<linux/ioport.h>/* For io-port access */
#include<linux/spinlock.h>/* For spin_lock/spin_unlock/.. */
#include<linux/uaccess.h>/* For copy_to_user/put_user/.. */
#include<linux/io.h>/* For inb/outb/.. */
#include<linux/platform_data/itco_wdt.h>
#include'iTCO_vendor.h'
/* Address definitions for the TCO */
/* TCO base address */
#defineTCOBASE(p) ((p)->tco_res->start)
/* SMI Control and Enable Register */
#defineSMI_EN(p) ((p)->smi_res->start)
#defineTCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
#defineTCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
#defineTCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
#defineTCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
#defineTCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
#defineTCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
#defineTCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
#defineTCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
#defineTCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
/* internal variables */
struct iTCO_wdt_private {
struct watchdog_device wddev;
/* TCO version/generation */
unsignedint iTCO_version;
struct resource *tco_res;
struct resource *smi_res;
/*
* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
* or memory-mapped PMC register bit 4 (TCO version 3).
*/
struct resource *gcs_pmc_res;
unsignedlong __iomem *gcs_pmc;
/* the lock for io operations */
spinlock_t io_lock;
/* the PCI-device */
struct pci_dev *pci_dev;
/* whether or not the watchdog has been suspended */
bool suspended;
/* no reboot API private data */
void *no_reboot_priv;
/* no reboot update function pointer */
int (*update_no_reboot_bit)(void *p, bool set);
};
/* module parameters */
#defineWATCHDOG_TIMEOUT30/* 30 sec default heartbeat */
staticint heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, 'Watchdog timeout in seconds. '
'5.76 (TCO v1) or 3.614 (TCO v2), default='
__MODULE_STRING(WATCHDOG_TIMEOUT) ')');
staticbool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
'Watchdog cannot be stopped once started (default='
__MODULE_STRING(WATCHDOG_NOWAYOUT) ')');
staticint turn_SMI_watchdog_clear_off = 1;
module_param(turn_SMI_watchdog_clear_off, int, 0);
MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
'Turn off SMI clearing watchdog (depends on TCO-version)(default=1)');
/*
* Some TCO specific functions
*/
/*
* The iTCO v1 and v2's internal timer is stored as ticks which decrement
* every 0.6 seconds. v3's internal timer is stored as seconds (some
* datasheets incorrectly state 0.6 seconds).
*/
staticinlineunsignedintseconds_to_ticks(struct iTCO_wdt_private *p,
int secs)
{
return p->iTCO_version3 ? secs : (secs * 10) / 6;
}
staticinlineunsignedintticks_to_seconds(struct iTCO_wdt_private *p,
int ticks)
{
return p->iTCO_version3 ? ticks : (ticks * 6) / 10;
}
staticinline u32 no_reboot_bit(struct iTCO_wdt_private *p)
{
u32 enable_bit;
switch (p->iTCO_version) {
case5:
case3:
enable_bit = 0x00000010;
break;
case2:
enable_bit = 0x00000020;
break;
case4:
case1:
default:
enable_bit = 0x00000002;
break;
}
return enable_bit;
}
staticintupdate_no_reboot_bit_def(void *priv, bool set)
{
return0;
}
staticintupdate_no_reboot_bit_pci(void *priv, bool set)
{
struct iTCO_wdt_private *p = priv;
u32 val32 = 0, newval32 = 0;
pci_read_config_dword(p->pci_dev, 0xd4, &val32);
if (set)
val32 = no_reboot_bit(p);
else
val32 &= ~no_reboot_bit(p);
pci_write_config_dword(p->pci_dev, 0xd4, val32);
pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
/* make sure the update is successful */
if (val32 != newval32)
return -EIO;
return0;
}
staticintupdate_no_reboot_bit_mem(void *priv, bool set)
{
struct iTCO_wdt_private *p = priv;
u32 val32 = 0, newval32 = 0;
val32 = readl(p->gcs_pmc);
if (set)
val32 = no_reboot_bit(p);
else
val32 &= ~no_reboot_bit(p);
writel(val32, p->gcs_pmc);
newval32 = readl(p->gcs_pmc);
/* make sure the update is successful */
if (val32 != newval32)
return -EIO;
return0;
}
staticvoidiTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
struct itco_wdt_platform_data *pdata)
{
if (pdata->update_no_reboot_bit) {
p->update_no_reboot_bit = pdata->update_no_reboot_bit;
p->no_reboot_priv = pdata->no_reboot_priv;
return;
}
if (p->iTCO_version >= 2)
p->update_no_reboot_bit = update_no_reboot_bit_mem;
elseif (p->iTCO_version1)
p->update_no_reboot_bit = update_no_reboot_bit_pci;
else
p->update_no_reboot_bit = update_no_reboot_bit_def;
p->no_reboot_priv = p;
}
staticintiTCO_wdt_start(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsignedint val;
spin_lock(&p->io_lock);
iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
/* disable chipset's NO_REBOOT bit */
if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
spin_unlock(&p->io_lock);
pr_err('failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOSn');
return -EIO;
}
/* Force the timer to its reload value by writing to the TCO_RLD
register */
if (p->iTCO_version >= 2)
outw(0x01, TCO_RLD(p));
elseif (p->iTCO_version1)
outb(0x01, TCO_RLD(p));
/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
val = inw(TCO1_CNT(p));
val &= 0xf7ff;
outw(val, TCO1_CNT(p));
val = inw(TCO1_CNT(p));
spin_unlock(&p->io_lock);
if (val & 0x0800)
return -1;
return0;
}
staticintiTCO_wdt_stop(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsignedint val;
spin_lock(&p->io_lock);
iTCO_vendor_pre_stop(p->smi_res);
/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
val = inw(TCO1_CNT(p));
val = 0x0800;
outw(val, TCO1_CNT(p));
val = inw(TCO1_CNT(p));
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
p->update_no_reboot_bit(p->no_reboot_priv, true);
spin_unlock(&p->io_lock);
if ((val & 0x0800) 0)
return -1;
return0;
}
staticintiTCO_wdt_ping(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
spin_lock(&p->io_lock);
/* Reload the timer by writing to the TCO Timer Counter register */
if (p->iTCO_version >= 2) {
outw(0x01, TCO_RLD(p));
} elseif (p->iTCO_version1) {
/* Reset the timeout status bit so that the timer
* needs to count down twice again before rebooting */
outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
outb(0x01, TCO_RLD(p));
}
spin_unlock(&p->io_lock);
return0;
}
staticintiTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsignedint t)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsignedint val16;
unsignedchar val8;
unsignedint tmrval;
tmrval = seconds_to_ticks(p, t);
/* For TCO v1 the timer counts down twice before rebooting */
if (p->iTCO_version1)
tmrval /= 2;
/* from the specs: */
/* 'Values of 0h-3h are ignored and should not be attempted' */
if (tmrval < 0x04)
return -EINVAL;
if ((p->iTCO_version >= 2 && tmrval > 0x3ff)
(p->iTCO_version1 && tmrval > 0x03f))
return -EINVAL;
/* Write new heartbeat to watchdog */
if (p->iTCO_version >= 2) {
spin_lock(&p->io_lock);
val16 = inw(TCOv2_TMR(p));
val16 &= 0xfc00;
val16 = tmrval;
outw(val16, TCOv2_TMR(p));
val16 = inw(TCOv2_TMR(p));
spin_unlock(&p->io_lock);
if ((val16 & 0x3ff) != tmrval)
return -EINVAL;
} elseif (p->iTCO_version1) {
spin_lock(&p->io_lock);
val8 = inb(TCOv1_TMR(p));
val8 &= 0xc0;
val8 = (tmrval & 0xff);
outb(val8, TCOv1_TMR(p));
val8 = inb(TCOv1_TMR(p));
spin_unlock(&p->io_lock);
if ((val8 & 0x3f) != tmrval)
return -EINVAL;
}
wd_dev->timeout = t;
return0;
}
staticunsignedintiTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsignedint val16;
unsignedchar val8;
unsignedint time_left = 0;
/* read the TCO Timer */
if (p->iTCO_version >= 2) {
spin_lock(&p->io_lock);
val16 = inw(TCO_RLD(p));
val16 &= 0x3ff;
spin_unlock(&p->io_lock);
time_left = ticks_to_seconds(p, val16);
} elseif (p->iTCO_version1) {
spin_lock(&p->io_lock);
val8 = inb(TCO_RLD(p));
val8 &= 0x3f;
if (!(inw(TCO1_STS(p)) & 0x0008))
val8 += (inb(TCOv1_TMR(p)) & 0x3f);
spin_unlock(&p->io_lock);
time_left = ticks_to_seconds(p, val8);
}
return time_left;
}
/*
* Kernel Interfaces
*/
staticconststruct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT
WDIOF_KEEPALIVEPING
WDIOF_MAGICCLOSE,
.firmware_version = 0,
.identity = DRV_NAME,
};
staticconststruct watchdog_ops iTCO_wdt_ops = {
.owner = THIS_MODULE,
.start = iTCO_wdt_start,
.stop = iTCO_wdt_stop,
.ping = iTCO_wdt_ping,
.set_timeout = iTCO_wdt_set_timeout,
.get_timeleft = iTCO_wdt_get_timeleft,
};
/*
* Init & exit routines
*/
staticintiTCO_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
struct iTCO_wdt_private *p;
unsignedlong val32;
int ret;
if (!pdata)
return -ENODEV;
p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
spin_lock_init(&p->io_lock);
p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
if (!p->tco_res)
return -ENODEV;
p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
if (!p->smi_res)
return -ENODEV;
p->iTCO_version = pdata->version;
p->pci_dev = to_pci_dev(dev->parent);
iTCO_wdt_no_reboot_bit_setup(p, pdata);
/*
* Get the Memory-Mapped GCS or PMC register, we need it for the
* NO_REBOOT flag (TCO v2 and v3).
*/
if (p->iTCO_version >= 2 && !pdata->update_no_reboot_bit) {
p->gcs_pmc_res = platform_get_resource(pdev,
IORESOURCE_MEM,
ICH_RES_MEM_GCS_PMC);
p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
if (IS_ERR(p->gcs_pmc))
returnPTR_ERR(p->gcs_pmc);
}
/* Check chipset's NO_REBOOT bit */
if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
iTCO_vendor_check_noreboot_on()) {
pr_info('unable to reset NO_REBOOT flag, device disabled by hardware/BIOSn');
return -ENODEV; /* Cannot reset NO_REBOOT bit */
}
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
p->update_no_reboot_bit(p->no_reboot_priv, true);
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
if (!devm_request_region(dev, p->smi_res->start,
resource_size(p->smi_res),
pdev->name)) {
pr_err('I/O address 0x%04llx already in use, device disabledn',
(u64)SMI_EN(p));
return -EBUSY;
}
if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
/*
* Bit 13: TCO_EN -> 0
* Disables TCO logic generating an SMI#
*/
val32 = inl(SMI_EN(p));
val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
outl(val32, SMI_EN(p));
}
if (!devm_request_region(dev, p->tco_res->start,
resource_size(p->tco_res),
pdev->name)) {
pr_err('I/O address 0x%04llx already in use, device disabledn',
(u64)TCOBASE(p));
return -EBUSY;
}
pr_info('Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)n',
pdata->name, pdata->version, (u64)TCOBASE(p));
/* Clear out the (probably old) status */
switch (p->iTCO_version) {
case5:
case4:
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
break;
case3:
outl(0x20008, TCO1_STS(p));
break;
case2:
case1:
default:
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
break;
}
p->wddev.info = &ident,
p->wddev.ops = &iTCO_wdt_ops,
p->wddev.bootstatus = 0;
p->wddev.timeout = WATCHDOG_TIMEOUT;
watchdog_set_nowayout(&p->wddev, nowayout);
p->wddev.parent = dev;
watchdog_set_drvdata(&p->wddev, p);
platform_set_drvdata(pdev, p);
/* Make sure the watchdog is not running */
iTCO_wdt_stop(&p->wddev);
/* Check that the heartbeat value is within it's range;
if not reset to the default */
if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
pr_info('timeout value out of range, using %dn',
WATCHDOG_TIMEOUT);
}
watchdog_stop_on_reboot(&p->wddev);
watchdog_stop_on_unregister(&p->wddev);
ret = devm_watchdog_register_device(dev, &p->wddev);
if (ret != 0) {
pr_err('cannot register watchdog device (err=%d)n', ret);
return ret;
}
pr_info('initialized. heartbeat=%d sec (nowayout=%d)n',
heartbeat, nowayout);
return0;
}
#ifdef CONFIG_PM_SLEEP
/*
* Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
* the watchdog cannot be pinged while in that state. In ACPI sleep states the
* watchdog is stopped by the platform firmware.
*/
#ifdef CONFIG_ACPI
staticinlineboolneed_suspend(void)
{
returnacpi_target_system_state() ACPI_STATE_S0;
}
#else
staticinlineboolneed_suspend(void) { returntrue; }
#endif
staticintiTCO_wdt_suspend_noirq(struct device *dev)
{
struct iTCO_wdt_private *p = dev_get_drvdata(dev);
int ret = 0;
p->suspended = false;
if (watchdog_active(&p->wddev) && need_suspend()) {
ret = iTCO_wdt_stop(&p->wddev);
if (!ret)
p->suspended = true;
}
return ret;
}
staticintiTCO_wdt_resume_noirq(struct device *dev)
{
struct iTCO_wdt_private *p = dev_get_drvdata(dev);
if (p->suspended)
iTCO_wdt_start(&p->wddev);
return0;
}
staticconststruct dev_pm_ops iTCO_wdt_pm = {
.suspend_noirq = iTCO_wdt_suspend_noirq,
.resume_noirq = iTCO_wdt_resume_noirq,
};
#defineITCO_WDT_PM_OPS (&iTCO_wdt_pm)
#else
#defineITCO_WDT_PM_OPSNULL
#endif/* CONFIG_PM_SLEEP */
staticstruct platform_driver iTCO_wdt_driver = {
.probe = iTCO_wdt_probe,
.driver = {
.name = DRV_NAME,
.pm = ITCO_WDT_PM_OPS,
},
};
staticint __init iTCO_wdt_init_module(void)
{
pr_info('Intel TCO WatchDog Timer Driver v%sn', DRV_VERSION);
returnplatform_driver_register(&iTCO_wdt_driver);
}
staticvoid __exit iTCO_wdt_cleanup_module(void)
{
platform_driver_unregister(&iTCO_wdt_driver);
pr_info('Watchdog Module Unloadedn');
}
module_init(iTCO_wdt_init_module);
module_exit(iTCO_wdt_cleanup_module);
MODULE_AUTHOR('Wim Van Sebroeck <wim@iguana.be>');
MODULE_DESCRIPTION('Intel TCO WatchDog Timer Driver');
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE('GPL');
MODULE_ALIAS('platform:' DRV_NAME);

Intel Pch Watchdog Controller Driver Windows 10

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